1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to a semiconductor memory device having data input/output frequency which is higher than internal operating frequency and capable of efficiently testing a data input/output circuit.
2. Description of the Background Art
In the last few years, the enhanced operating frequency of the microprocessor requires increased data bandwidth of a semiconductor memory device. Techniques which have been published for increasing the data bandwidth are to double the width of the data bus, to enhance clock frequency of a synchronous semiconductor memory device and the like. As a technique for enhancing data frequency, a synchronous semiconductor memory device has been proposed which inputs/outputs data synchronously with both of the rising and falling of a clock signal. Further, a high speed interface technique has been published which makes the frequency of a synchronous clock used for supplying and receiving input/output data to and from any external unit at least four times as high as internal operating frequency of a synchronous semiconductor memory device.
Description is herein presented on a structure of a data input/output circuit in a semiconductor memory device having its data input/output frequency which is four times as high as internal operating frequency.
FIG. 15 is a block diagram showing a structure of a data input/output circuit 100 of a semiconductor memory device having its data input/output frequency which is four times as high as internal operating frequency.
Referring to FIG. 15, data input/output circuit 100 inputs and outputs four consecutive data DQ via a one-bit data terminal 10 synchronously with external clock signal ext.CLK which is supplied to a clock terminal 16.
Data input/output circuit 100 operates in synchronization with internal clock signals CLKD and CLKQ and internal frequency-divided clock signals clkA to clkD which are generated by an internal clock generating circuit 30.
Data input/output circuit 100 includes an S/P data conversion circuit 130 which converts serial input data Din supplied via a data input buffer 115 into parallel data synchronously with internal frequency-divided clock signals clkA to clkD to transmit them to four write data lines WDa to WDd, and a write circuit 162 which writes the input data transmitted to write data lines WDa to WDd into a memory cell array 50 in parallel in response to activation of write control signal WE.
Data input/output circuit 100 further includes a read circuit 164 which reads four data in parallel from memory cell array 50 to transmit them to read data lines RDa to RDd, a P/S data conversion circuit 140 which converts four parallel data into serial data Dout in synchronization with internal frequency-divided clock signals clkA to clkD, and a data output buffer 120 which supplies output data Dout of a P/S data conversion circuit 140 to data terminal 10.
Data input/output circuit 100 thus makes an internal serial-parallel conversion of serial data which are input and output from the data terminal and performs reading and writing operations of the parallel data all together from and into the memory cell array so as to enhance the data input/output frequency relative to the internal operating frequency.
An operation of data input/output circuit 100 is now described in conjunction with a timing chart.
FIG. 16 is the timing chart illustrating a data input operation carried out by data input/output circuit 100.
Referring to FIG. 16, in the data input operation, four consecutive data D0 to D3 are supplied to one-bit data terminal 10 synchronously with both of the falling and rising of external clock signal ext.CLK.
Internal clock generating circuit 30 responds to external clock signal ext.CLK to generate internal clock signal CLKD. Internal clock signal CLID is activated in response to both of the rising and falling of external clock signal ext.CLK and has its frequency two times as high as the external clock signal. In response to activation of internal clock signal CLKD, input data DQ supplied to the data terminal is taken by the data input buffer.
Internal clock generating circuit 30 further generates internal frequency-divided clock signals clkA to clkD by dividing the frequency of internal clock signal CLKD. The frequency of internal frequency-divided clock signals clkA to clkD is half the frequency of internal clock signal CLKD and the phases thereof are shifted by one cycle of internal clock signal CLKD.
S/P data conversion circuit 130 operates in response to internal frequency-divided clock signals clkA to clkD to transmit input data D0 to D3 to write data lines WDa to WDd respectively at time t0 to time t3. Accordingly, the four input data consecutively supplied to one-bit data terminal 10 undergo serial-parallel conversion to become four-bit parallel data which are transmitted by four internal write data lines.
After time t3 at which the fourth input data D3 is transmitted to write data line WDd, at time t4, write control signal WE is activated and write circuit 162 transmits the data transmitted to write data lines WDa to WDd to memory cell data lines MIOa to MIOd respectively. The four-bit parallel data are thus written into the memory cell array simultaneously.
The frequency of write control signal corresponds to the internal operating frequency of the synchronous semiconductor memory device. The frequency of internal clock signal CLKD which is the data input frequency is seen four times as high as the internal operating frequency.
A problem which arises when the data input/output frequency becomes high is described below.
FIG. 17 is a timing chart illustrating data input timing when the data input/output frequency is equal to the internal operating frequency.
Referring to FIG. 17, in response to activation of external clock signal ext.CLK at time t0, data D2 transmitted to the data terminal is input.
In this case, setup time Ts and hold time Th are ensured respectively, and thus there is a relatively large margin for data input/output timing.
FIG. 18 is a timing chart illustrating data input timing when the data input frequency is four times as high as the internal operating frequency.
Referring to FIG. 18, the data input frequency is defined as four times as high as that illustrated in FIG. 17. Therefore, when data D2 is input in response to activation of external clock signal ext.CLK at time to, setup time and hold time are ensured to correspond to only ts and th respectively as shown.
If the data input frequency is increased, the setup and hold time for data relative to the clock signal are shortened, resulting in decrease in margin of data input/output timing. Accordingly, a resultant problem is increase in rate of defect occurrence in the data input/output circuit. It is then required to do an efficient operation test by immediately detecting any defect in the data input/output circuit.
In a conventional synchronous semiconductor memory device, a data input/output circuit operates at a low frequency which is identical to that of an internal clock signal used as a reference for an internal operation. Therefore, defect is rarely found in the data input/output circuit and thus a dedicated test circuit for the data input/output circuit is unnecessary.
However, if the data input/output frequency is increased and the possibility of occurrence of defect in the data input/output circuit becomes higher, it takes a long time to discover the cause of the defect and an efficient operation test could become impossible unless a dedicated circuit for testing the data input/output circuit is provided.
The present invention is made to solve the problems as described above. One object of the present invention is to provide a structure of a semiconductor memory device, which operates at a data input/output frequency higher than an internal operating frequency, so as to enable an operation test of a data input/output circuit to be done efficiently.
According to one aspect of the present invention, a semiconductor memory device is provided which internally converts serial data supplied to and from any external unit into parallel data and performs reading and writing operations thereof. The semiconductor memory device includes a memory cell array, a data terminal and a data input/output circuit.
The memory cell array includes a plurality of memory cells arranged in rows and columns. The data terminal inputs and outputs N data (N: natural number) which are transmitted in time series manner. The data input/output circuit includes, for the memory cell array, N write data lines and N read data lines provided for writing and reading N data and transmitting N data in parallel, a first data conversion circuit which converts N serial data input from the data terminal into N parallel data to transmit them to the write data lines, a second data conversion circuit which converts N parallel data transmitted by the read data lines into N serial output data to be output from the data terminal, a read and write circuit for supplying and receiving N data all together between N write data lines and the memory cell array and between N read data lines and the memory cell array, and an input/output test circuit which transfers data transmitted by N write data lines respectively to N read data lines in an input/output test operation.
According to another aspect of the invention, a semiconductor memory device is provided which internally converts serial data supplied to and from any external unit into parallel data and performs reading and writing operations thereof. The semiconductor memory device includes a memory cell array, a plurality of data terminals, a plurality of data input/output circuits and a plurality of input/output test circuits.
The memory cell array includes a plurality of memory cells arranged in rows and columns. A plurality of data terminals each independently input and output N data (N: natural number) which are transmitted in time series manner. A plurality of data input/output circuits are arranged respectively for the data terminals and each read and write N data from and into the memory cell array. Each of the data input/output circuits includes N write data lines and N read data lines for transmitting N data in parallel, a first data conversion circuit which converts N serial data supplied from an associated one of the data terminals into N parallel data to transmit them to the write data lines, a second data conversion circuit which converts N parallel data transmitted by the read data lines into N serial output data to be output from the associated data terminal, and a read and write circuit for supplying and receiving N data all together between N write data lines and the memory cell array and between N read data lines and the memory cell array.
A plurality of input/output test circuits are each arranged between one of the data input/output circuits and another one of the data input/output circuits to transfer, in an input/output test operation, data transmitted by N write data lines included in the one of the data input/output circuits respectively to N read data lines included in the another one of the data input/output circuits.
According to still another aspect of the invention, a semiconductor memory device is provided which internally converts serial data supplied to and from any external unit into parallel data and performs reading and writing operations thereof The semiconductor memory device includes a memory cell array, a plurality of data terminals, a control circuit, a plurality of data input/output circuits and an input/output test circuit.
The memory cell array includes a plurality of memory cells arranged in rows and columns. A plurality of data terminals each independently input and output N data (N: natural number) which are transmitted in time series manner. The control circuit generates L control signals (L: natural number) for controlling timing of the reading and writing operations. A plurality of data input/output circuits are arranged respectively for the data terminals and each read and write N data from and into the memory cell array. Each of the data input/output circuits includes N write data lines and N read data lines for transmitting N data in parallel, a first data conversion circuit which converts N serial data input from an associated one of the data terminals into N parallel data to transmit them to the write data lines, a second data conversion circuit which converts N parallel data transmitted from the read data lines into N serial data to be output from the associated data terminal, a read and write circuit for supplying and receiving N data all together between N write data lines and the memory cell array and between N data read lines and the memory cell array, and an output buffer circuit for outputting. data of the second data conversion circuit to the associated one of the data terminals in the reading operation, and outputting test data to the associated one of the data terminals in an input/output test operation. The input/output test circuit transmits as test data, in the input/output test operation, N data transmitted by N write data lines included in one of the data input/output circuits and M control signals (M: natural number equal to or less than L) respectively to the output buffer circuits respectively included in remaining N+M data input/output circuits among the data input/output circuits.
A principal advantage of the present invention is that the input/output circuit can be tested without performing data reading and writing from and into a memory cell so that the input/output circuit can be tested without using a memory tester.
Further, since the input/output circuit can be tested using at least N consecutive data trains, evaluation of a test such as evaluation of operating frequency is possible regarding data input in a memory system configured by using the semiconductor memory device.
In addition, in input/output test operation, control signals and data signals can be output from the data terminals, so that inappropriate timing of the control signals can be detected.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.